In most microcomputer applications, the microcomputer device is operated from a fixed frequency clock source that is typically a crystal oscillator circuit contained within the microcomputer circuitry. This configuration makes the structure of the microcomputer's timing circuitry simple, but it can limit the desired performance of the microcomputer system in terms of power drain and programming flexibility. In addition, this arrangement can also impact the overall cost of the microcomputer system.
In applications in which the computational requirements vary with time, the clock frequency must necessarily be set high enough to provide the computational power (computations/second) required to handle the most demanding task to be performed by the microcomputer. In these applications, the computer frequently operates at higher clock frequencies than would be required to perform the less demanding immediate tasks. Since all microcomputers, and especially CMOS microcomputers, dissipate more power at high operating frequencies than at low operating frequencies, it follows that CMOS microcomputers driven by the conventional fixed frequency clock signal source dissipate more power than they would if the clock frequency could be raised and lowered in accordance with the demands of the immediate tasks. This would greatly aid in reducing the power dissipation of the system and in addition, if the clock frequency were under program control, this would provide a more energy efficient microcomputer system.
One prior art system which attempts to reduce the adverse effects of these problems uses a programmable divider connected between a crystal oscillator clock source and the microcomputer. The modulus of the divider can be changed to provide either a high frequency or a low frequency clock signal input to the microcomputer in an effort to reduce the power dissipation of the microcomputer. However, here again, the base frequency of the crystal oscillator must be high enough to operate the microcomputer at the highest clock frequency required to handle the computational requirements of the most difficult of the preprogrammed tasks. Admittedly, some energy savings occurs when the microcomputer is operated at a lower clock frequency. But, the divider circuitry which enables reduction of the clock frequency is always operating at a high input clock frequency, and the power drain of the divider itself, together with the power drain of the high frequency oscillator, can severely impact the power drain of the total microcomputer system. In fact, in many applications in which there is a very large difference between the required minimum and maximum clock frequencies for microcomputer tasks, the crystal oscillator and programmable divider in combination draw significantly more power than would the microcomputer in its lower frequency, lower power drain mode. In addition, a problem exists in the fact that the operating frequency of most microprocessor crystal oscillators is in the range of from 1.0 MHz to 8.0 MHz. The crystal frequency control elements that are available in this range of frequencies are large in size and relatively expensive when compared to the much smaller low cost, low frequency (30 kHz to 100 kHz) crystals that have been developed primarily for electronic time piece applications. Thus there are substantial size, power and cost problems associated with the utilization of prior art apparatus.